Intel CONTROLLERS 413808 - Manual (Page 527)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 527
SRAM Memory Controller—Intel
®
413808 and 413812
8.3.3.5 ECC Disabled
If software disables ECC, the SMCU does generate the ECC byte for writes, but does not
check the ECC byte for reads.
8.3.3.6 ECC Testing
Section 8.3.3.4, “Scrubbing” on page 526 explains how software is responsible for
correcting an error in the memory array once it has been detected by the ECC logic.
The SMCU implements the SECTST register providing the programmer the ability to
test error handling software. For write transactions, the SECTST register value is
XORed with the generated ECC. This inverts the bits where the mask is set prior to
writing the ECC to memory. When the SMCU reads the address later, the ECC
mismatches and the error condition occurs (see Section 8.4, “ECC Interrupts/Error
Conditions” on page 531 ).