Intel CONTROLLERS 413808 - Manual (Page 486)

Intel
®
413808 and 413812—System Controller (SC) and Internal Bus Bridge
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
486 Order Number: 317805-001US
7.2 Theory of Operation
7.2.1 System Controller
The XSI System Controller (SC) is the arbiter for the XSI bus. There is one SC for the
North XSI bus and one for the South XSI bus since there are two XSI busses on
4138xx. The XSI bus supports fully demultiplex and independent address and data
paths, thus the SC performs arbitration for address requests and data requests
separately. Up to 15 agents are supported by the SC.
For address request arbitration, the SC receives address bus request from each
requesting agent seeking to master requests on the address bus and implements an
arbitration algorithm to generate address bus grant to grant the bus to a particular
requesting agent. The SC actually frames the address transactions, and therefore
drives the address strobe along with the address bus grant. The assertion of address
strobe indicates that a valid XSI bus command is driven the following cycle.
For data request arbitration, the SC receives data bus request from each requesting
agent seeking to master a data transaction on the data bus and implements an
arbitration algorithm to generate data bus grant to grant the data bus to a particular
requesting agent. The SC frames the data transactions, and therefore initiates the data
transaction along with the data bus grant.
The SC ORs several bus outputs from each agent and routes the ORed signals back to
each agent, including the Address Qualifier Signals (AQS) and Data Qualifier Signals
(DQS).
Both the address and data bus arbiters support simple round-robin algorithms. Each
internal bus initiator can be individually enabled or disabled. When an initiator is
disabled, any address request made by that initiator is not granted the internal bus.
Each arbiter parks on the last master.