Intel CONTROLLERS 413808 - Manual (Page 403)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 403
Messaging Unit—Intel
®
413808 and 413812
4.3 Message Registers
Messages can be sent and received by the 4138xx through the use of the Message
Registers. When written, the message registers may cause an interrupt to be generated
to either the Intel XScale
®
processor or the host processor. Inbound messages are sent
by the host processor and received by the 4138xx. Outbound messages are sent by the
4138xx and received by the host processor.
The interrupt status for outbound messages is recorded in the Outbound Interrupt
Status Register. Interrupt status for inbound messages is recorded in the Inbound
Interrupt Status Register.
4.3.1 Outbound Messages
When an outbound message register is written by the Intel XScale
®
processor, an
interrupt may be generated on the P_INTA# interrupt pins or a message signaled
interrupt is generated when MSI is enabled.
The PCI interrupt is recorded in the Outbound Interrupt Status Register. The interrupt
causes the Outbound Message Interrupt bit to be set in the Outbound Interrupt Status
Register. This is a Read/Clear bit that is set by the MU hardware and cleared by
software.
The interrupt is cleared when an external PCI agent writes a value of 1 to the Outbound
Message Interrupt bit in the Outbound Interrupt Status Register to clear the bit.
The interrupt may be masked by the mask bits in the Outbound Interrupt Mask
Register.
4.3.2 Inbound Messages
When an inbound message register is written by an external PCI agent, an interrupt
may be generated to the Intel XScale
®
processor. The interrupt may be masked by the
mask bits in the Inbound Interrupt Mask Register.
The Intel XScale
®
processor interrupt is recorded in the Inbound Interrupt Status
Register. The interrupt causes the Inbound Message Interrupt bit to be set in the
Inbound Interrupt Status Register. This is a Read/Clear bit that is set by the MU
hardware and cleared by software.
The interrupt is cleared when the Intel XScale
®
processor writes a value of 1 to the
Inbound Message Interrupt bit in the Inbound Interrupt Status Register.