Intel CONTROLLERS 413808 - Manual (Page 726)

Intel ® 413808 and 413812—General Purpose I/O Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
726 Order Number: 317805-001US
15.2.2 GPIO Input Data Register — GPID
The GPIO Input Data Register reflects the state of the appropriate GPIO bus pins
following the deassertion of P_RST# .
Table 479. GPIO Input Data Register — GPID (Sheet 1 of 2)
Bit Default Description
31:16 0000H Reserved
15
GPIO[15]
during
P_RST#
assertion
GPIO15 Input Data — This bit reflects the state of the GPIO[15] pin.
14
GPIO[14]
during
P_RST#
assertion
GPIO14 Input Data — This bit reflects the state of the GPIO[14] pin.
13
GPIO[13]
during
P_RST#
assertion
GPIO13 Input Data — This bit reflects the state of the GPIO[13] pin.
12
GPIO[12]
during
P_RST#
assertion
GPIO12 Input Data — This bit reflects the state of the GPIO[12] pin.
11
GPIO[11]
during
P_RST#
assertion
GPIO11 Input Data — This bit reflects the state of the GPIO[11] pin.
10
GPIO[10]
during
P_RST#
assertion
GPIO10 Input Data — This bit reflects the state of the GPIO[10] pin.
09
GPIO[9]
during
P_RST#
assertion
GPIO9 Input Data — This bit reflects the state of the GPIO[9] pin.
08
GPIO[8]
during
P_RST#
assertion
GPIO8 Input Data — This bit reflects the state of the GPIO[8] pin.
07
GPIO[7]
during
P_RST#
assertion
GPIO7 Input Data — This bit reflects the state of the GPIO[7] pin.
06
GPIO[6]
during
P_RST#
assertion
GPIO6 Input Data — This bit reflects the state of the GPIO[6] pin.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Local Bus Address
offset
+2484H