Intel CONTROLLERS 413808 - Manual (Page 630)

Intel ® 413808 and 413812—Timers
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
630 Order Number: 317805-001US
11.1.3 Load/Store Access Latency for Timer Registers
As with all other load accesses from internal memory-mapped registers, a load
instruction that accesses a timer register has a latency of one internal processor cycle.
With one exception, a store access to a timer register completes and all state changes
take effect before the next instruction begins execution. The exception to this is when
disabling a timer. Latency associated with the disabling action is such that a timer
interrupt may be posted immediately after the disabling instruction completes. This can
occur when the timer is near zero as the store to TMRx occurs. In this case, the timer
interrupt is posted immediately after the store to TMRx completes and before the next
instruction can execute. Table 417 summarizes the timer access and response timings.
Refer also to the individual register descriptions for details.
Note that the processor may delay the actual issuing of the load or store operation due
to previous instruction activity and resource availability of processor functional units.
The processor ensures that the TMRx.tc bit is cleared within one internal bus clock after
a load or store instruction accesses TMRx.
Table 417. Timer Responses to Register Bit Settings
Name Status Action
(TMRx.tc)
Terminal Count
Bit 0
READ
Timer clears this bit when user software accesses TMRx. This bit can be set 1
internal bus clock later. The timer sets this bit within 1 internal bus clock of
TCRx reaching zero when TMRx.reload=0.
WRITE
Timer clears this bit within 1 internal bus clock after the software accesses
TMRx. The timer ignores any value specified for TMRx.tc in a write request.
(TMRx.enable)
Timer Enable
Bit 1
READ
Bit is available 1 internal bus clock after executing a read instruction from
TMRx.
WRITE
Writing a ‘1’ enables the internal bus clock to decrement TCRx within 1
internal bus clock after executing a store instruction to TMRx.
(TMRx.reload)
Timer Auto Reload
Enable
Bit 2
READ
Bit is available 1 internal bus clock after executing a read instruction from
TMRx.
WRITE
Writing a ‘1’ enables the reload capability within 1 internal bus clock after the
store instruction to TMRx has executed. The timer loads TRRx data into TCRx
and decrements this value during the next internal bus clock cycle.
(TMRx.csel1:0)
Timer Input Clock
Select
Bits 4-5
READ
Bits are available 1 internal bus clock after executing a read instruction from
TMRx.csel1:0 bit(s).
WRITE
The timer re-synchronizes the clock cycle used to decrement TCRx within one
internal bus clock cycle after executing a store instruction to TMRx.csel1:0
bit(s).
(TCRx.d31:0)
Timer Count
Register
READ
The current TCRx count value is available within 1 internal bus clock cycle
after executing a read instruction from TCRx. When the timer is running, the
pre-decremented value is returned as the current value. When the timer is
transferring the TRRx count into TCRx in the current count cycle, the timer
returns the new TCRx count value to the executing read instruction.
WRITE
The value written to TCRx becomes the active value within 1 internal bus
clock cycle. When the timer is running, the value written is decremented in
the current clock cycle.
(TRRx.d31:0)
Timer Reload
Register
READ
The current TRRx count value is available within 1 internal bus clock after
executing a read instruction from TRRx.
WRITE
The value written to TRRx becomes the active value stored in TRRx within 1
internal bus clock cycle. When the timer is transferring the TRRx value into
the TCRx, data written to TRRx is also transferred into TCRx.