Intel CONTROLLERS 413808 - Manual (Page 594)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
594 Order Number: 317805-001US
05 0
2
XINT13# Interrupt Mask. Source of this interrupt is the GPIO[5] pin.
0 = Masked
1 = Not Masked
04 0
2
XINT12# Interrupt Mask. Source of this interrupt is the GPIO[4] pin.
0 = Masked
1 = Not Masked
03 0
2
XINT11# Interrupt Mask. Source of this interrupt is the GPIO[3] pin.
0 = Masked
1 = Not Masked
02 0
2
XINT10# Interrupt Mask. Source of this interrupt is the GPIO[2] pin.
0 = Masked
1 = Not Masked
01 0
2
XINT9# Interrupt Mask. Source of this interrupt is the GPIO[1] pin.
0 = Masked
1 = Not Masked
00 0
2
XINT8# Interrupt Mask. Source of this interrupt is the GPIO[0] pin.
0 = Masked
1 = Not Masked
Table 392. Interrupt Control Register 1 — INTCTL1 (Sheet 2 of 2)
Bit Default Description
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, Page 4, Register 1