Intel CONTROLLERS 413808 - Manual (Page 542)

Intel
®
413808 and 413812—SRAM Memory Controller
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
542 Order Number: 317805-001US
8.6.8 SRAM Parity Control and Status Register — SPARCSR
This register programs the SMCU parity checking capabilities. This register is also
responsible for logging the error types detected on the SMCU memory ports. Only one
error can be detected and logged. The error recorded corresponds to the addresses in
(SPAR, SPUAR) and (SPCAR, SPCUAR).
The status bits are read-only bits and only have meaning if SMCISR[8] is non-zero. For
more details, see Section 8.3.4, “Byte Parity Checking and Generation” on page 528
and Section 8.5, “Parity Interrupts/Error Conditions” on page 534 .
Table 357. SRAM Parity Control and Status Register — SPARCSR
Bit Default Description
31:24 00H Reserved
23:20 0000
2
Parity Error Requester: Indicates the requester of the logged error:
Internal Bus Requester ID Requester Name
0000
2
Reserved
0001
2
Intel XScale ® processor 0 (coreID0)
0010
2
Intel XScale ® processor 1 (coreID1)
0011
2
ATUX
0100
2
ATUE
0101
2
Application DMAs
0110
2
Reserved
0111
2
Messaging Unit
1000
2
Reserved
1001
2
SMBus
All other IDs are reserved.
Note: This field is only valid when the Port ID in this register (bits[19:16]) indicates the north internal
bus as the memory port.
Note: Not all of the Requesters can or will access the SRAM Memory.
19:16 0000
2
Direct Memory Port ID: Indicates the direct memory port associated with the parity error:
Port ID Port Name
0000
2
North Internal Bus
0001
2
Reserved
0010
2
Reserved
0011
2
Reserved
0100
2
Reserved
0101
2
Reserved
0110
2
Reserved
0111
2
Reserved
1000
2
Reserved
1001
2
Reserved
1010
2
Reserved
All other Port IDs are reserved.
15:01 0000H Reserved
00 0
2
SMCU Parity Enabled: Enables or disables checking, logging, and reporting (interrupt generation) of
parity errors on the memory ports.
0 = Disable Parity Error
1 = Enable Parity Error
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Local Bus Address Offset
+151CH