Intel CONTROLLERS 413808 - Manual (Page 345)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 345
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
2 0
Fatal Error Reporting Enable – This bit in conjunction with other bits control sending ERR_FATAL
messages. For a multi-function device, this bit controls error reporting for each function from the
point-of-view of the respective function.
For a Root Port, the reporting of fatal errors is internal to the root. No external ERR_FATAL message is
generated.
1 0
Non-Fatal Error Reporting Enable – This bit in conjunction with other bits controls sending
ERR_NONFATAL messages. For a multi-function device, this bit controls error reporting from the
point-of-view of the respective function.
For a Root Port, the reporting of non-fatal errors is internal to the root. No external ERR_NONFATAL
message is generated.
0 0
Correctable Error Reporting Enable – This bit in conjunction with other bits controls sending ERR_COR
messages. For a multi-function device, this bit controls error reporting from the point-of-view of the
respective function.
For a Root Port, the reporting of correctable errors is internal to the root. No external ERR_COR
message is generated.
Table 199. PCI Express Device Control Register - PE_DCTL (Sheet 2 of 2)
Bit Default Description
PCI
IOP
Attributes
Attributes
15 12 8 4 0
pr
pr
rw
rw
rw
rw
rw
rw
rw
rw
ro
ro
ro
ro
ro
ro
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+0D8H