Intel CONTROLLERS 413808 - Manual (Page 245)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 245
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.3.2.1 Outbound Address Translation - Internal Bus Transactions
In addition to providing the mechanism for inbound translation, the ATU translates Intel
XScale
®
processor-initiated cycles to the PCI Express domain. This is known as
outbound address translation. Outbound transactions are processor or DMA
transactions targeted at the PCI Express Link. The ATU internal bus target interface
claims internal bus cycles and completes the cycle on the PCI Express Link on behalf of
the Intel XScale
®
processor or DMAs.
Figure 26 shows 4 Gbyte memory section 0 (Internal Bus Address [35:32] = 0000
2
) of
the 4138xx memory map with all reserved address locations highlighted. The 64KByte
outbound I/O window is from 0.FFFD.0000H to 0.FFFD.FFFFH while the PMMR registers
reside from 0.FFD8.0000H to 0.FFDF.FFFFH.
By default, Outbound Memory Window 0, Outbound Memory Window 1, Outbound
Memory Window 2, and Outbound Memory Window 3reside in 4 Gbyte memory
sections 1, 2, 3, and 4respectively, of the 64 Gbyte Internal Bus address space.
The response of the ATU to Outbound Transactions is globally controlled by the
Outbound Enable bit in the ATU Configuration Register as well as the Bus Master Enable
bit in each function. When the Outbound Enable bit is deasserted, outbound transaction
master-abort on the internal bus and are not forwarded to the PCI Express Domain.
When the Outbound Enable bit is asserted, the relevant Bus Master Enable bit for each
function is used to determine the appropriate response to an outbound transaction.
The Outbound ATUs behavior for the different combinations of these control bits is
described in Table 122 .
Table 122. Outbound Address Translation Control
Outbound Response Outbound Enable
a
(ATUCR[1])
a. In addition, the outbound memory windows need to be individually enabled in order to claim the transaction.
When the memory widow is disabled, it does not claim a transaction which might result in a Master-Abort. By
default, Outbound Memory Windows 0 and 1 are enabled while Outbound Memory Windows 2, and 3 are
disabled.
Bus Master Enable
b
b. In a multi-function configuration, each function independently controls its own Bus Master Enable bit.
Master-Abort 0 0
Master-Abort 0 1
Retry 1 0
Claim c
c. The ATU may respond with a Retry in this case when the Outbound Transaction Queues are full.
1 1