7 sram ecc test register - sectst, Table 356. sram ecc test register - sectst, 7 sram ecc test register — sectst – Intel CONTROLLERS 413808 User Manual
Page 541: 356 sram ecc test register — sectst, Table 356. sram ecc test register — sectst, Bit default description
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
541
SRAM Memory Controller—Intel
®
413808 and 413812
8.6.7
SRAM ECC Test Register — SECTST
This register allows testing between the SRAM ECC logic and the memory subsystem
Section 8.3.3.6, “ECC Testing” on page 527
). To test error handling software, the
programmer writes this register with a non-zero masking function. Any subsequent
writes to memory stores a masked version of the computed ECC. Therefore, any
subsequent reads to these locations result in an ECC error.
Table 356. SRAM ECC Test Register — SECTST
Bit
Default
Description
31:07
00 0000H
Reserved
06:00
00H
ECC Mask: 7-bit ECC mask. Each bit of the generated ECC is XORed with the appropriate bit in this
mask field before the ECC is stored into memory. See
Section 8.3.3.6, “ECC Testing” on page 527
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale
®
processor Local Bus Address Offset
+1518H