Intel CONTROLLERS 413808 - Manual (Page 586)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
586 Order Number: 317805-001US
10.7.4 FIQ Interrupt Vector Register — FINTVEC
The FIQ Interrupt Vector Register is a 32-bit Coprocessor 6 control register. Following
an FIQ exception, the FIQ interrupt service routine reads the 32-bit vector to the ISR
for the active FIQ source with the highest priority.
The actual vector value is a function of the INTBASE and the INTSIZE registers and is
based on a fixed order of all 128 possible interrupt sources. The vectors begin at
INTBASE with source 0 (i.e., FINTSRC0 bit 0), and end at INTBASE + INTSIZE (per
source)*127 with source 127 (that is, FINTSRC3 bit 31).
Before returning to User Mode from Interrupt Mode, the software reads the FINTVEC
register and process any lower priority FIQ sources that are active. When there are no
longer any active FIQ sources, a read from the FINTVEC register returns FFFF FFFFH.
Table 386. FIQ Interrupt Vector Register- FINTVEC
Bit Default Description
31:00 00000000H FIQ Interrupt Vector—Vector to the highest priority active FIQ source. This register reads FFFF FFFFH
when there are no active FIQ sources.
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, Page 2, Register 4