Intel CONTROLLERS 413808 - Manual (Page 592)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
592 Order Number: 317805-001US
14 0
2
ATU-E Inbound Message Interrupt Mask
0 = Masked
1 = Not Masked
13 0
2
Messaging Unit Inbound Post Queue Interrupt Mask
0 = Masked
1 = Not Masked
12 0
2
Messaging Unit Interrupt Mask
0 = Masked
1 = Not Masked
1 =
11 0
2
I 2 C Bus Interface 1 Interrupt Mask
0 = Masked
1 = Not Masked
10 0
2
I 2 C Bus Interface 0 Interrupt Mask
0 = Masked
1 = Not Masked
9 0
2
Timer 1 Interrupt Mask
0 = Masked
1 = Not Masked
8 0
2
Timer 0 Interrupt Mask
0 = Masked
1 = Not Masked
7 0
2
Reserved.
6 0
2
Watch Dog Timer Interrupt Mask
0 = Masked
1 = Not Masked
5 0
2
Reserved.
4 0
2
Reserved.
3 0
2
Reserved.
2 0
2
Reserved.
1 0
2
Reserved.
0 0
2
Reserved.
Table 391. Interrupt Control Register 0 — INTCTL0 (Sheet 2 of 2)
Bit Default Description
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, Page 4, Register 0