Intel CONTROLLERS 413808 - Manual (Page 381)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 381
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.102 Outbound Configuration Cycle Address Register - OCCAR
The Outbound Configuration Cycle Address Register is used to hold bytes 8-11 of the
configuration transaction header. The Intel XScale
®
processor writes the bus, device,
function, and register number which then enables the outbound configuration read or
write. The Intel XScale
®
processor then performs a read or write to the Outbound
Configuration Cycle Data Register to initiate the configuration transaction on the PCI
Express Link.
Table 242. Outbound Configuration Cycle Address Register - OCCAR
Bit Default Description
31:24 00H Bus Number
23:19 00H Device Number
18:16 000b Function Number
15:12 0H Reserved
11:8 0H Extended Register Number
7:2 00H Register Number
1 0H Reserved
0 0
Configuration Type
0 = Generate Type 0 Configuration TLP
1 = Generate Type 1 Configuration TLP
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rv
ro
rv
ro
rv
ro
rv
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rv
ro
rw
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+32CH