Intel CONTROLLERS 413808 - Manual (Page 326)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
326 Order Number: 317805-001US
3.17.40 ATU Configuration Register - ATUCR
The ATU Configuration Register contains some additional parameters in the ATU.
Table 180. ATU Configuration Register - ATUCR
Bit Default Description
31 0 Reserved
30 0
Completion Timeout Disable. - When set, this bit disables the completion timeout mechanism for
outbound non-posted requests. Read/Write.
29:09 0 Reserved
08 0
Halt on Error. - When enabled, an Address or Data Parity an Outbound write request results in the
follow actions:
• Stop accepting outbound requests by clearing the outbound enable.
• Flush any pending outbound write requests from the transaction queue that are behind the one
that had the error.
• Assert the Halt On Error Interrupt to the Intel XScale ® Processor.
• Assert the appropriate error interrupt to the Intel XScale ® Processor.
• Read requests is allowed to proceed normally though no new ones is accepted.
07 0 Reserved
06 1
Drop subsequent inbound vendor defined messages (IVM).
0 = When cleared, subsequent IVMs remains in the inbound posted queue and blocks all other
transactions.
1 = When set and the inbound vendor defined message registers are full with a pending IVM,
subsequent IVMs is discarded. This is necessary to prevent a deadlock condition when the Intel
XScale ® processor needs to receive a read completion before it can handle the IVM interrupt.
05 0
Outbound Completion Size - This bit controls how completions are returned on the PCI Express
interface.
0 = Max Payload Size setting is used to format completions. Once enough data has accumulated to
reach a Max Payload address boundary, the completion TLP is formed and pushed into the
completion queue. Completion TLPs has a payload size of 128, 256, or 512 bytes depending on the
setting of the Max_Payload_Size field in the “PCI Express Device Control Register - PE_DCTL” on
page 344 .
1 = 128B Payload Size. All completions uses a maximum size of 128 bytes regardless of the setting of
the Max_Payload_Size field.
04 0
Inbound Minimum Completion Size - This bit controls how completion data is returned to the internal
bus.
0 = Return completion data as it is received from the PCI Express interface. This size may be as small
as 64Bytes.
1 = Wait for the entire request to be satisfied before returning completion data.
03 0
ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale ® processor when the
start BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 in the
ATUBISTR register.
02 0
2
Reserved
01 0
2
Outbound ATU Enable - When set, enables the outbound address translation unit. When cleared,
disables the outbound ATU.
Note: Transport Firmware always sets the bit to 1. Do no clear this bit.
00 0
2
Reserved
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
rv
rv
rw
rw
rw
rw
rw
rw
rw
rw
rv
rv
rw
rw
rv
rv
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+070H