3 uart x interrupt enable register, 449 uart x interrupt enable register - (uxier), Uarts—intel – Intel CONTROLLERS 413808 User Manual
Page 671: Bit default description
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
671
UARTs—Intel
®
413808 and 413812
13.4.3
UART x Interrupt Enable Register
This register enables six types of interrupts which set a value in the Interrupt
Identification register. Each of the six interrupt types can be disabled by clearing the
appropriate bit of the IER register. Similarly, by setting the appropriate bits, selected
interrupts can be enabled.
This register also has the control bits of the unit enable and NRZ coding enable. The
use of bit 7 to bit 4 is different from the register definition of standard 16550.
Note:
A global interrupt enable/disable exists in the Modem Control Register bit 3 (IE). After
reset, this bit must be set or no interrupts occurs, regardless of the state of the IER
bits. See
Section 13.4.7, “UART x Modem Control Register” on page 678
.
Table 449. UART x Interrupt Enable Register - (UxIER)
Bit
Default
Description
31:8
00 0000h
Reserved
7
0
2
Preserved
6
0
2
UART Unit Enable (UUE):
0 = the unit is disabled
1 = the unit is enabled
5
0
2
NRZ coding Enable (NRZE):
0 = NRZ coding disabled
1 = NRZ coding enabled
4
0
2
Receiver Time Out Interrupt Enable: (RTOIE)
0 = Receiver data Time out Interrupt disabled
1 = Receiver data Time out Interrupt enabled
3
0
2
Modem Interrupt Enable (MIE):
0 = Modem Status interrupt disabled
1 = Modem Status interrupt enabled
2
0
2
Receiver Line Status Interrupt Enable (RLSE):
0 = Receiver Line Status interrupt disabled
1 = Receiver Line Status interrupt enabled
1
0
2
Transmit Data request Interrupt Enable (TIE):
0 = Transmit FIFO Data Request interrupt disabled
1 = Transmit FIFO Data Request interrupt enabled
0
0
2
Receiver Data Available Interrupt Enable (RAVIE):
0 = Receiver Data Available (Trigger level reached) interrupt disabled
1 = Receiver Data Available (Trigger level reached) interrupt enabled
PC
I
IO
P
A
tt
ri
bu
te
s
A
tt
ri
bu
te
s
28
24
20
16
12
8
4
0
31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
pr
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
Unit #
01
Intel XScale
®
Core internal bus address
+2304H (DLAB=x)
+2344H (DLAB=x)
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible