Intel CONTROLLERS 413808 - Manual (Page 569)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 569
Interrupt Controller Unit—Intel
®
413808 and 413812
10.4 Intel
®
413808 and 413812 I/O Controllers in TPER Mode
External Interrupt Interface
The interrupt controller attached to the Intel XScale
®
processor has the facilities
necessary to handle all core processor and peripheral internal interrupts as well as the
sixteen external interrupts ( XINT[15:0]# ) and a high priority interrupt ( HPI# ).
The 4138xx Primary PCI local bus interface includes four interrupt output signals
( XINT[3:0]# / P_INT[D:A]# ). Interrupts from the Messaging Unit and Address
Translation Units are routed to these interrupt output signals.
10.4.1 Interrupt Inputs
The 17 external interrupt input pins of the 4138xx have the following definitions:
XINT[3:0]# External Interrupt (Input) — These pins ( XINT[3:0]# ) cause
interrupts to be requested. Each pin is a level-detect input only. These
pins are internally synchronized. These pins act as interrupt inputs and
must be unmasked in the INTCTL[3:0] registers. These pins also act as
interrupt outputs ( P_INT[D:A]# ) for the PCI-X interface when
configured as an endpoint. These pins can also function as general
purpose inputs/outputs ( GPIO[11:8] ) when not used as interrupt pins.
XINT[7:4]# External Interrupt (Input) — These pins ( XINT[7:4]# ) cause
interrupts to be requested. Each pin is a level-detect input only. These
pins are internally synchronized. These pins only act as interrupt inputs
when they are unmasked in the INTCTL[3:0] registers. These pins can
also function as general purpose inputs/outputs ( GPIO[15:12] ) when
not used as interrupt pins.
XINT[15:8]# External Interrupt (Input) — These pins ( XINT[15:8]# ) cause
interrupts to be requested. Each pin is a level-detect input only. These
pins are internally synchronized. These pins only act as interrupt inputs
when they are configured as general purpose inputs and are unmasked
in the INTCTL[3:0] registers. These pins can also function as general
purpose inputs/outputs ( GPIO[7:0] ) when not used as interrupt pins.
HPI# High-Priority Interrupt (Input) — Causes a high priority interrupt
event to occur. The external HPI# input requires a level input and is
maskable by the INTCTL[3:0] registers. This pin is internally
synchronized.
NMI0# Non-Maskable Interrupt 0 (Input) — Causes a non-maskable
imprecise data abort exception to the Intel XScale
®
processor 0. The
external NMI0# input requires a falling edge triggered input. This pin is
internally synchronized.
NMI1# Non-Maskable Interrupt 1 (Input) — Causes a non-maskable
imprecise data abort exception to the Intel XScale
®
processor 1. The
external NMI1# input requires a falling edge triggered input. This pin is
internally synchronized.
Note: NMI0# and NMI1# are not implemented as part of the Interrupt Controller Units.
They are external pins which are falling edge triggered, internally synchronized and
then directly driven to the respectively Intel XScale
®
processors.