Intel CONTROLLERS 413808 - Manual (Page 221)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 221
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.83 PCI Interface Error Address Register - PCIEAR
When PCIECSR bit 0 is set, this register represents the lower 32-bits of the address for
the error detected on the PCI Bus. Note that for a DAC cycle the address may be 64-bit.
This register is used in conjunction with Section 2.14.84, “PCI Interface Error Upper
Address Register - PCIEUAR” on page 222 in order to interpret the entire 64-bit PCI
address for the error. One error can be detected and logged. The software knows which
PCI address had the error by reading this register and decoding the contents of the
PCIECSR. For error details, see Section 2.7, “ATU Error Conditions” on page 94 ).
Note: The “PCI Interface Error Control and Status Register - PIECSR” , “PCI Interface Error
Address Register - PCIEAR” , and “PCI Interface Error Upper Address Register -
PCIEUAR” report the original transaction when an error is detected on the current
transaction. For example, when the Split Completion of an original Outbound Read
request had an error, the information regarding the Outbound Read is reported.
Table 110. PCI Interface Error Address Register - PCIEAR
Bit Default Description
31:00 0000 0000H
Error Address: When PCIECSR bit 0 is set, this register represents the lower 32-bits of the PCI
Address.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+384H