Intel CONTROLLERS 413808 - Manual (Page 787)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 787
Test Logic Unit and Testability—Intel ® 413808 and 413812
18.2.2.5 Shift-DR State
In this controller state, the test data register, which is connected between TDI and
TDO as a result of the current instruction, shifts data one bit position nearer to its
serial output on each rising edge of TCK . Test data registers that the current instruction
select but do not place in the serial path, retain their previous value during this state.
The instruction does not change while the TAP controller is in this state.
Transition to next state: When
TMS is high on the rising edge of TCK , move to
Exit1-DR, else remain at Shift-DR.
18.2.2.6 Exit1-DR State
This is a temporary controller state.
All test data registers selected by the current instruction retain their previous value
during this state. The instruction does not change while the TAP controller is in this
state.
Transition to next state: When
TMS is held high on the rising edge of TCK , the
controller enters the Update-DR state and the scanning process terminates. When
TMS is held low on the rising edge of TCK , the controller enters the Pause-DR state.
18.2.2.7 Pause-DR State
The Pause-DR state allows the test controller to temporarily halt the shifting of data
through the test data register in the serial path between TDI and TDO .
All test data registers selected by the current instruction retain their previous value
during this state. The instruction does not change while the TAP controller is in this
state.
Transition to next state: When
TMS is high on the rising edge of TCK , move to the
Exit2-DR, else remain at Pause-DR.
18.2.2.8 Exit2-DR State
This is a temporary state.
All test data registers selected by the current instruction retain their previous value
during this state. The instruction does not change while the TAP controller is in this
state.
Transition to next state: When
TMS is high on the rising edge of TCK , the controller
enters the Update-DR state and the scanning process terminates. When TMS is held
low on the rising edge of TCK , the controller re-enters the Shift-DR state
18.2.2.9 Update-DR State
Data is latched into the parallel output of shift registers from the shift register path, on
the falling edge of TCK .
All of the test data register’s shift-register bit positions selected by the current
instruction retain their previous values. The instruction does not change while the TAP
controller is in this state.
Transition to next state: When
TMS remains high on the rising edge of TCK , then the
controller moves to the Select-DR state, else the controller moves to the Run-Test/Idle
state.