Intel CONTROLLERS 413808 - Manual (Page 58)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
58 Order Number: 317805-001US
Figure 6 shows an inbound translation example for 32-bit addressing. This example
would hold true for an inbound transaction from PCI bus.
Figure 6. Inbound Translation Example
0000 0000H
FFFF FFFFH
0 0000 0000H
F FFFF FFFFH
Base_Register = 3A00 0000H
Limit_Register = FF80 0000H (8 Mbyte limit value)
Inbound
Window
Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes)
PCI_Address
Value_Register = B100 0000H
Internal_Bus
Address
PCI Address
Space
I/O Processor Local
Memory Address Space
Address Detection (32-bit address)
PCI_Address and Limit_Register == Base_Register
3A45 012CH and FF80 0000H == 3A00 0000H
3A45 012CH
PCI_Address is in the Inbound Translation Window
Address Translation
IB_Address = (PCI_Address and ~Limit_Register) | Value_Register
IB_Address = ((3A45 012CH and 007F FFFFH) | B100 0000H) | (1H << 32)
1 B145 012CH
Register Values
IB_Address = 1 B145 012CH
Upper_Value_Register = 1H
Translation
B6323-01