Intel CONTROLLERS 413808 - Manual (Page 795)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 795
Peripheral Registers—Intel ® 413808 and 413812
19.2 Accessing Peripheral Memory-Mapped Registers
The PMMR interface is a slave device connected to the 4138xx internal bus. This
interface accepts data transactions which appear on the internal bus from the ATU and
the Intel XScale
®
processors.
The PMMR interface allows these devices to perform read, write, or read-modify-write
transactions. The specific actions taken when modifying any value in the PMMR space is
independently defined within each chapter which describes the functionality of the
register.
Note: The PMMR interface does not support multi-word burst accesses from any internal bus
master.
All PMMR transactions are allowed from the Intel XScale
®
processors operating in user
or supervisor mode. In addition, the PMMR does not provide any access exception to
the Intel XScale
®
processor.
19.3 Accessing Peripheral Registers Using the Core
Coprocessor Register Interface
Registers may be accessed/manipulated through the CCR interface with the MCR, MRC,
STC, and LDC instructions. The CRn field of the instruction denotes the register number
to be accessed. The opcode_1,and opcode_2 fields of the instruction should be zero.
The CRm field must be set to 0 for the Interrupt Controller Unit and to 1 for the
Programmable Timers. Most systems restrict access to coprocessor registers to
privileged processes. To control access to a coprocessor register, use the Coprocessor
Access Register as described in the ARM Architecture Reference Manual.
19.4 Architecturally Reserved Memory Space
The 4138xx provides 64 GBytes of address space. Portions of this address space is
architecturally reserved and users are restricted as to their function. Figure 124 shows
the reserved address space.
Addresses 0 0000 0000H through 0 0000 001FH are reserved for the exception vectors
of the Intel XScale
®
processor.
Addresses 0 FFFF 0000H through 0 FFFF 001FH are reserved for the relocated
exception vectors of the Intel XScale
®
processor.
Addresses 0 FFD8 0000H through 0 FFDF FFFFH are allocated to the PMMR interface by
default. These registers cannot be relocated for the 4138xx in any mode.