Figure 4. atu queue architecture block diagram, 4 atu queue architecture block diagram, Intel – Intel CONTROLLERS 413808 User Manual
Page 52
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Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
52
Order Number: 317805-001US
Figure 4.
ATU Queue Architecture Block Diagram
PC
IB
us
In
te
rn
al
B
us
In
te
rf
ac
e
PC
IB
us
In
te
rfa
ce
ADDRESS TRANSLATION UNIT
In
te
rn
al
B
us
OWQ 4 KBytes
OWADQ
OTQ
IWQ 4 KBytes
IRQ 4 KBytes
IDWQ
(1 entry)
ITQ (8entries)
(8 entries)
(4 entries)
IWADQ
(4 entries)
ORQ 2 or 4 KBytes
B6321-01
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