Intel CONTROLLERS 413808 - Manual (Page 108)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
108 Order Number: 317805-001US
2.7.4.3 Outbound Read Completion Correctable Data Errors
As a target device, when an outbound read completion correctable data error is
detected, the following actions are taken:
• The error is corrected and the ATU completes the transaction on the PCI bus as
when no error had occurred. Then, the transaction is forwarded to the internal bus
normally.
• Update the “ECC Control and Status Register - ECCCSR” on page 195 , the “ECC
First Address Register - ECCFAR” on page 198 , the “ECC Second Address Register -
ECCSAR” on page 199 , and the “ECC Attribute Register - ECCAR” on page 200 for
the transaction.
— When the ATU Detected Correctable Error Interrupt Mask bit in the ATUIMR is
clear, set the Detected Correctable Error bit in the ATUISR. When set, no
action.
2.7.4.4 Inbound Configuration Write Request
As a target device, when an inbound configuration write request correctable data error
is detected, the following actions are taken:
• The error is corrected and the ATU completes the transaction on the PCI bus as
when no error had occurred. Then, the transaction is forwarded to the internal bus
normally.
• Update the “ECC Control and Status Register - ECCCSR” on page 195 , the “ECC
First Address Register - ECCFAR” on page 198 , the “ECC Second Address Register -
ECCSAR” on page 199 , and the “ECC Attribute Register - ECCAR” on page 200 for
the transaction.
— When the ATU Detected Correctable Error Interrupt Mask bit in the ATUIMR is
clear, set the Detected Correctable Error bit in the ATUISR. When set, no
action.
2.7.4.5 Split Completion Messages
As a target device, when a split completion message correctable data error is detected,
the following actions are taken:
• The error is corrected and the ATU completes the transaction on the PCI bus as
when no error had occurred. Then, the transaction is forwarded to the internal bus
normally.
• Update the “ECC Control and Status Register - ECCCSR” on page 195 , the “ECC
First Address Register - ECCFAR” on page 198 , the “ECC Second Address Register -
ECCSAR” on page 199 , and the “ECC Attribute Register - ECCAR” on page 200 for
the transaction.
— When the ATU Detected Correctable Error Interrupt Mask bit in the ATUIMR is
clear, set the Detected Correctable Error bit in the ATUISR. When set, no
action.