Intel CONTROLLERS 413808 - Manual (Page 277)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 277
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
Malformed TLP
Receiver:
Send ERR_FATAL/
ERR_NONFATAL
to Root Complex
Log the header of the
TLP that caused the
error.
ADVERR_CTL
ADVERR_LOGx
PIE_CSR
PIE_LOGx
PIE_DLOG
ATUSR[14]
PE_DSTS[2 or 1]
ERRUNC_STS[18]
PIE_STS[18]
ATUISR[10, 8]
ATUCMD[8]
PE_DCTL[2 or 1]
ATUIMR[8]
ERRUNC_MSK[18]
PIE_MSK[18]
Physical Layer Errors
Receiver Error
Send ERR_COR
to Root Complex
PE_DSTS[0]
ERRCOR_STS[0]
ATUISR[9]
PE_DCTL[0]
ATUIMR[9]
Training Error
Send ERR_FATAL/
ERR_NONFATAL
to Root Complex
PIE_CSR
PE_DSTS[2 or 1]
ERRUNC_STS[0]
PIE_STS[0]
ATUISR[8]
ATUCMD[8]
PE_DCTL[2 or 1]
ATUIMR[8]
Data Link Layer Errors
Bad TLP
Receiver:
Send ERR_COR
to Root Complex
PE_DSTS[0]
ERRCOR_STS[6]
ATUISR[9]
PE_DCTL[0]
ERRCOR_MSK[6]
ATUIMR[9]
Bad DLLP
Receiver:
Send ERR_COR
to Root Complex
PE_DSTS[0]
ERRCOR_STS[7]
ATUISR[9]
PE_DCTL[0]
ERRCOR_MSK[7]
ATUIMR[9]
Replay Timeout
Transmitter:
Send ERR_COR
to Root Complex
PE_DSTS[0]
ERRCOR_STS[12]
ATUISR[9]
PE_DCTL[0]
ERRCOR_MSK[12]
ATUIMR[9]
REPLAY_NUM
Rollover
Transmitter:
Send ERR_COR
to Root Complex
PE_DSTS[0]
ERRCOR_STS[8]
ATUISR[9]
PE_DCTL[0]
ERRCOR_MSK[8]
ATUIMR[9]
Data Link Layer
Protocol Error
Send ERR_FATAL/
ERR_NONFATAL
to Root Complex
PIE_CSR
PE_DSTS[2 or 1]
ERRUNC_STS[4]
PIE_STS[4]
ATUISR[10, 8]
ATUCMD[8]
PE_DCTL[2 or 1]
ATUIMR[8]
ERRUNC_MSK[4]
PIE_MSK[4]
Device Specific Errors
Received
Completion with
UR status
None
PIE_CSR
PIE_LOG[3:0]
PIE_DLOG
ATUSR[13]
PIE_STS[31]
ATUISR[10, 3]
ATUIMR[3]
PIE_MSK[31]
Received
Completion with
CA status
None
PIE_CSR
PIE_LOG[3:0]
PIE_DLOG
ATUSR[12]
PIE_STS[30]
ATUISR[10, 1]
ATUIMR[1]
PIE_MSK[30]
Poisoned TLP
Transmitted
None
PIE_CSR
PIE_LOG[3:0]
PIE_DLOG
ATUSR[8]
PIE_STS[29]
ATUISR[10, 0]
ATUIMR[0]
PIE_MSK[29]
Outbound Header
Parity Error
detected
None
PIE_CSR
PIE_LOG[3:0]
PIE_DLOG
PIE_STS[28] ATUISR[10] PIE_MSK[28]
a. ERR_FATAL / ERR_NONFATAL action is determined by the severity bits in the ERRUNC_SEV register.
Table 135. PCI Express Error Summary (Sheet 2 of 2)
Error Condition
Bus Protocol
Action
a
Affected
Logging
Register
Affected bits in
Unit Status
Register
Affected bits in
Interrupt Status
Register
Unit Interrupt
Mask Bits