Intel CONTROLLERS 413808 - Manual (Page 134)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
134 Order Number: 317805-001US
2.12.6 Bus Mode and Frequency Initialization
The ATUs PCI Bus interface is capable of operating at a variety of frequencies, and in
either Conventional PCI mode, or in PCI-X mode. The bus mode is established when
coming out of the bus segment reset sequences. When the ATUs central resource is
enabled, the resultant mode and frequency is dependent upon the device capabilities
reported as well as any system specific loading information.
The ATU, as the central resource is the originating device for the PCI bus and as such,
sets the bus mode and frequency when exiting out of the bus reset sequence. The two
key components that factor into the resultant secondary bus mode and frequency are
the PCI-X standard sampling of downstream device capabilities, and the system specific
physical bus loading characteristics for which the PCI-X Protocol Addendum to the PCI
Local Bus Specification, Revision 2.0 does not provide any standard means of
reporting.
Downstream device capabilities are indicated by the values of
P_M66EN , and
P_PCIXCAP during P_RST# assertion.
Note: Knowledge of the device capabilities alone is insufficient information to robustly select
the bus frequency. In order to be sure of what the bus operating frequency should be
set to, knowledge of the bus layout (e.g., number of slots), is necessary.
When, for example, a 133 MHz PCI-X capable adapter was the sole occupant of a two
slot segment, then it would be necessary to slow the bus to 100 MHz, even though the
card reported it could operate at 133 MHz due to the additional electrical loading
imposed by the two slot board and connector layout.
The ATU provides a strapping approach for reporting system specific bus loading
information that is used in determining the maximum operating frequency of the
secondary bus. The ATU considers this strap along with the device capabilities reported
during P_RST# to determine the PCI bus's mode and frequency when emerging from
P_RST# .
This strap, entitled PCI-X Bus 100 MHz Enable, is sampled on PCIXM1_100# ,
indicating to the ATU what to limit the bus frequency to a maximum of 100MHz. The
value of this field is determined by the system designer, after having assessed the
characteristics of the PCI bus system/adapter implementation.
Table 23. Device Mode/Frequency Capability Reporting
M66EN PCIXCAP
a
a. Resistor values are specified in Section 2.3.4, “PCIXCAP and MODE2 Connection,” in PCI-X Electrical and
Mechanical Addendum to the PCI Local Bus Specification, Revision 2.0.
Conventional PCI
Device Frequency
Capability
PCI-X Device
Frequency Capability
Ground Ground 33 MHz Not capable
8.2K pull-up b
b. M66EN may be pulled high on the motherboard.
Ground 66 MHz Not capable
Ground 10K Pull-down 33 MHz PCI-X 66 MHz
8.2K pull-up b 10K Pull-down 66 MHz PCI-X 66 MHz
Ground NC 33 MHz PCI-X 133 MHz
8.2K pull-up b NC 66 MHz PCI-X 133 MHz
Ground 3.16K 1% pull-down 33 MHz PCI-X 266 MHz
8.2K pull-up b 3.16K 1% pull-down 66 MHz PCI-X 266 MHz