Intel CONTROLLERS 413808 - Manual (Page 530)

Intel
®
413808 and 413812—SRAM Memory Controller
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
530 Order Number: 317805-001US
8.3.4.2 Parity Checking
The direct memory port interface of the SMCU only checks data parity while receiving
data. The direct memory port interface verifies data parity on the port interface, and
then generates ECC before writing the data to memory. Table 347 lists the data bits
that are used for the parity calculation. The parity bits are calculated by bit XORing the
data bits as shown in Table 347 . As an example, the parity calculation for the lowest
order byte of the data bus D[7:0] is calculated as follows:
Note: The direct memory port does not support address parity.
Equation 16.DATA_PARITY_RESULT = D_PARITY0 XOR D[0] XOR D[1] XOR D[2] XOR D[3]
XOR D[4] XOR D[5] XOR D[6] XOR D[7] XOR BE[0]
A non-zero result from the above operation indicates a parity error.
The parity logic uses the following algorithm, and this algorithm logs the error if an
error is detected.
check data parity
if data parity result is good
done
else {error}
create an error log
Interrupt the core (if enabled)
8.3.4.3 Parity Disabled
If software disables parity, the SMCU would generate data parity as explained above,
but would not check and report data parity on the interface.
8.3.4.4 Parity Testing
The System Controller provides the ability for the programmer to test error handling
software by forcing address or data parity error. Refer to the Chapter 6.0, “System
Controller (SC) and Internal Bus Bridge” for more details.