Intel CONTROLLERS 413808 - Manual (Page 43)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 43
Introduction—Intel
®
413808 and 413812
Figure 2 is a block diagram of the 4138xx.
Figure 2. Intel
®
413808 and 413812 I/O Controllers in TPER Mode Functional Block
Diagram
P CI-X
Intel® 413808 and 413812 I/O Controllers
B6617-01 16-Bit I/F I 2 C Bus
72-Bit
I/F
SAS
Serial Bus
Serial Bus
Bridge
Host Interface
(ATU)
One TDMA
and
One SDMA
Multi-Port
SRAM
Memory
Controller
Two
UARTs
Three I 2 C
Bus
Interface
APB
PBI
Unit
(Flash)
SAS 0 PHY
SAS 1 PHY
SAS 7 PHY
Intel
XS cale®
Processor
(coreID = 0H)
512K L2 Cache
T imers Intel
XS cale®
Processor
(coreID = 1H)
512K L2 Cache
Inter-Core
Interrupt
Interrupt
Controller
Timers
Inter-Core
Interrupt
Interrupt
Controller
SMBus
Unit
SMBus
128-Bit South Internal Bus
128-Bit North Internal Bus
SAS
Serial Bus
PCI-E
Host Interface
(ATU)
IMU
DDR
not available in
TPER