Intel CONTROLLERS 413808 - Manual (Page 299)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 299
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.6 ATU Status Register - ATUSR
The ATU Status Register bits adhere to the PCI Local Bus Specification, Revision 2.3
definitions. The read/clear bits can only be set by internal hardware and cleared by
either a reset condition or by writing a 1
2
to the register.
Table 145. ATU Status Register - ATUSR
Bit Default Description
15 0
2
Detected Parity Error - set when the ATU receives a poisoned TLP regardless of the state of the Parity
Error Response in the ATUCMD register.
14 0
2
SERR# Asserted - set when the ATU sends an ERR_FATAL or ERR_NONFATAL message, and the SERR
Enable bit in the ATUCMD register is ‘1’.
13 0
2
Received Master Abort - set when the ATU receives a completion with Unsupported Request Completion
Status.
12 0
2
Received Target Abort - set when the ATU receives a completion with Completer Abort Completion
Status.
11 0
2
Signaled Target Abort - set when the ATU completes a Request using Completer Abort Completion
Status
10:09 00
2
DEVSEL# Timing - Does not apply to PCI Express.
Hard-wired to 0.
08 0
2
Master Data Parity Error - This bit is set by the ATU when its Parity Error Enable bit is set and either of
the following two conditions occurs:
This bit is set under the following conditions.
• ATU receives a Poisoned Completion for an Outbound Read Request
• ATU transmits a Poisoned TLP for an Outbound Write Request.
When the Parity Error Response bit is cleared in the “ATU Command Register - ATUCMD” , this bit is
never set.
07 0
2
Fast Back-to-Back - Does not apply to PCI Express.
Hard-wired to 0.
06 0
2
Reserved
05 0
2
66 MHz. Capable - Does not apply to PCI Express.
Hard-wired to 0
04 1
2
Capabilities List - All PCI Express devices are required to implement the PCI Express capability
structure.
Hard-wired to 1.
03 0
2
Interrupt Status - Indicates that an INTx interrupt message is pending internally to the device.
Note: Setting the Interrupt Disable bit to a 1 in (bit 10 of ATUCMD) has no effect on the state of this
bit.
02:00 000
2
Reserved
PCI
IOP
Attributes
Attributes
15 12 8 4 0
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
ro
ro
ro
ro
rc
rc
ro
ro
rv
rv
ro
ro
ro
ro
ro
ro
rv
rv
rv
rv
rv
rv
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+006H