2 outbound transactions, Section – Intel CONTROLLERS 413808 User Manual

Page 244

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Intel

®

413808 and 413812—Address Translation Unit (PCI Express)

Intel

®

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

244

Order Number: 317805-001US

3.3.2

Outbound Transactions

Outbound transactions initiated by the 4138xx core processor are directed to the PCI

Express interface through the ATU. As a PCI Express requester, the ATU is capable of

memory, I/O, configuration, and message transactions. Outbound memory transactions

with addresses below 4GB use the short address format (32-bit address). Addresses

above 4GB use the long address format (64-bit).
Outbound transactions use a separate set of queues from inbound transactions.

Outbound write operations have their address entered into the outbound posted header

queue (OPHQ) and their data into the outbound posted data queue (OPDQ). Outbound

read transactions, use the Outbound Non-Posted Queue (ONPQ) to store address, and

get data returned into the Inbound Completion Data Queue (ICPLDQ). Refer to

Section 3.8.2

for details of outbound queue architecture. Outbound configuration

transactions use a special outbound port structure and are enqueue in the ONPQ. Refer

to

Section 3.3.3

for details.

For outbound write transactions, the ATU is a target on the internal bus and a requester

on the PCI Express Link. For outbound read transactions, the ATU is a completer on the

internal bus (initially accepts the split read as a target and then provides read data by

initiating a split completion). Internal bus operation is defined in

Section 7.0, “System

Controller (SC) and Internal Bus Bridge”

.

Note:

For all outbound writes, the byte enables must be contiguous. This means that write

coalescing must be disabled in the Intel XScale

®

microarchitecture for transactions that

target the outbound memory windows.
While Outbound I/O transactions are supported in all configurations, they should only

be used when operating as the root complex. The PCI Express Specification states that

PCI Express Endpoints must not generate I/O requests.

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