Intel CONTROLLERS 413808 - Manual (Page 641)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 641
SMBus Interface Unit—Intel ® 413808 and 413812
12.0 SMBus Interface Unit
This chapter describes the SMBus (System Management Bus) interface unit, including
the operation modes and setup. Throughout this manual, this peripheral is referred to
as the SMBus unit.
12.1 Overview
The SMBus Interface Units allows the Intel
®
413808 and 413812 I/O Controllers in
TPER Mode (4138xx) to serve as a slave device residing on the SMBus. The SMBus is a
two-pin interface. SMBDAT is the data pin for input and output functions and SMBCLK
is the clock pin for reference and control of the SMBus.
The SMBus allows the system to interface to 4138xx for system management
functions. The serial bus requires a minimum of hardware for an economical system to
relay status and reliability information of the 4138xx to the system.
The SMBus Interface Unit is a peripheral device that resides on a 4138xx internal bus.
Data is transmitted to and received from the SMBus via a buffered interface. Control
and status information is relayed through a set of registers. Refer to the SMBus
Specification for complete details on SMBus operation.
12.2 SMBus Interface
SMBus provides for full access to registers in 4138xx including configuration and
memory-mapped registers. Systems so configured can use the SMBus to access the
registers. 4138xx supports a slave-only SMBus mode.
• System Management Bus Specification, Revision 2.0 (SMBus) Compliant.
• Slave mode operation only.
• Full read/write access to configuration and memory-mapped register spaces in
4138xx.
Table 428. SMBus Interface Pins
Signal Pad Type
SMBCLK SMBus Clock: Provides synchronous operation of the SMBus
.
SMBDAT SMBus Data: Used for data transfer and arbitration of the SMBus
.
Total 2