7 register definitions – Intel CONTROLLERS 413808 User Manual
Page 410
Intel
®
413808 and 413812—Messaging Unit
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
410
Order Number: 317805-001US
4.7
Register Definitions
The following registers are located in the Host I/O Interface address space and in the
Peripheral Memory-Mapped Register (PMMR) address space. They are accessible
through host I/O interface bus transactions and through Intel XScale
®
processor
internal bus accesses. In the Host I/O Interface address space, they are mapped into
the first 80 bytes of the inbound address window of the ATU.
• Inbound Message 0 Register
• Inbound Message 1 Register
• Outbound Message 0 Register
• Outbound Message 1 Register
• Inbound Doorbell Register
• Inbound Interrupt Status Register
• Inbound Interrupt Mask Register
• Outbound Doorbell Register
• Outbound Interrupt Status Register
• Outbound Interrupt Mask Register
• Inbound Reset Control and Status Register
• Outbound Reset Control and Status Register
• MSI Inbound Message Register
The following registers are located in the Peripheral Memory-Mapped Register (PMMR)
address space as described in
Chapter 19.0, “Peripheral Registers”
.
• MU Configuration Register
• MU Base Address Register
• MU Upper Base Address Register
Reading or writing a register that is reserved is undefined.