Intel CONTROLLERS 413808 - Manual (Page 485)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 485
System Controller (SC) and Internal Bus Bridge—Intel
®
413808 and 413812
7.0 System Controller (SC) and Internal Bus Bridge
This chapter describes the System Controllers (SC) of the Intel
®
413808 and 413812
I/O Controllers (4138xx). The System Controller controls the internal bus and its
agents. There are two System Controllers on 4138xx since there are two internal
busses.
7.1 Overview
The System Controller controls the internal bus agents arbitrating for the internal bus.
The Internal Bus on 4138xx contains a separate address bus arbiter and data bus
arbiter as the address and data busses are completely de-multiplexed. There are two
internal busses on 4138xx and therefore there are two system controllers implemented
— one for the North Internal Bus and one for the South Internal Bus.
• The north internal bus SC controls the two Intel XScale
®
processors, the DDR
Memory Controller, the Bridge, and the SAS Interface.
• The south internal bus SC controls the ATU-E, ATU-X, the Bridge, the DDR SDRAM
Memory Controller, the Application DMAs, the PBI, and the APB interface.
In addition to providing the address bus and data bus arbitration functionality, the SC
also initiates address and data transactions once the bus has been granted. The SC is
also the central hub which takes as inputs all the agents address and data busses, and
then controlling how the address bus or data bus is routed to an agent.
The SC also provides hardware functionality that can be used to force address and data
parity errors. This feature allows software to test error handling routines by forcing
address or data parity error.