Intel CONTROLLERS 413808 - Manual (Page 183)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 183
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.43 ATU Interrupt Mask Register - ATUIMR
The ATU Interrupt Mask Register contains the control bit to enable and disable
interrupts generated by the ATU.
Table 70. ATU Interrupt Mask Register - ATUIMR (Sheet 1 of 2)
Bit Default Description
31:16 0 0000H Reserved
15 0
2
PCI Interface Error Mask - Controls the setting of bit 18 of the ATUISR and generation of the PCI Interface
error when any PCI bus error occurs.
0 = Not Masked
1 = Masked
14 0
2
VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the
ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register.
0 = Not Masked
1 = Masked
13 0
2
Internal Bus Parity Error Detected Mask - Controls the setting of bit 16 of the ATUISR and generation of
the ATU Error interrupt when an internal bus parity error is detected.
0 = Not Masked
1 = Masked
12 0
2
Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the ATU
Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register
except those covered by mask bit 11 and bit 14 of this register.
0 = Not Masked
1 = Masked
11 1
2
Detected Correctable Error Mask - Controls setting of bit 14 of the ATUISR and generation of the
Correctable Error interrupt when in PCI-X Mode 2, a correctable error is detected in any phase of a PCI
transaction.
0 = Not Masked
1 = Masked
10 0
2
Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and
generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message.
0 = Not Masked
1 = Masked
09 0
2
Received Split Completion Error Message Interrupt Mask- Controls setting of bit 12 of ATUISR and
generation of ATU Error interrupt when a Split Completion Error Message results in bit 29 of PCIXSR being
set.
0 = Not Masked
1 = Masked
08 1
2
Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the
ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the ATU
Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0.
0 = Not Masked
1 = Masked
07 0
2
ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of
the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR.
0 = Not Masked
1 = Masked
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rv
rw
rw
rw
rv
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+07CH