Intel CONTROLLERS 413808 - Manual (Page 781)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 781
Clocking and Reset—Intel ® 413808 and 413812
EXT_ARB#
External Arbiter: Determines wether the PCI interface enables the integrated
arbiter, or uses an external arbiter.
0 = External Arbiter enabled (Requires pull-down resistor)
1 = Internal Arbiter enabled (Default mode)
PCIX_32BIT#
32-Bit PCI-X Bus
:
Sets the PCI-X bus width in the PCI-X Status Register. When this
external strap is asserted, the Sunrise lake only uses the lower 32-bit of the data
bus to operate and respond to PCI-X transactions. When the strap is deasserted
the 81348 is able to operate and respond to both 32- and 64-bit PCI-X
transactions.
This external strap also controls how the REQ64# signal is driven when the ATU-X
is used as central resource. As a central resource, REQ64# is driven accordingly
based on the PCIX_32BIT# strap setting during the assertion of P_RSTOUT#.
When PCIX_32BIT# is asserted REQ64# is driven high, and when PCIX_32BIT# is
deasserted REQ64# is driven low.
0 = 32 Bit PCI-X Bus (Requires pull-down resistor)
1 = 64 Bit PCI-X Bus (Default mode)
HS_SM#
Hot-Swap Startup Mode
0 = Hot-Swap Mode Enabled (Requires pull-down resistor)
1 = Hot-Swap Mode Disabled (default mode)
SMB_A5
SMB_A3
SMB_A2
SMB_A1
SMBUS Address maps to address bits 5, 3, 2, and 1 of the SMBus Slave address.
0 = Address is low (Requires Pull-down resistor)
1 = Address is high (Default mode).
PCIX_PULLUP#
PCI-X Pull Up: determines when the PCI interface has On Die Pull Ups enabled.
0 = enable PCI pull up resistors
1 = disable PCI pull up resistors (Default mode).
FW_TIMER_OFF#
Firmware Timer Off: Disables the 400mS firmware timer. When enabled to timer
automatically clears the Configuration Cycle Retry condition when the timer
expires.
0 = firmware timer disabled
1 = firmware timer enabled (default mode)
CLK_SRC_PCIE#
Clock Source PCI-Express: selects the PCI-Express REFCLK pair as the input clock
to the PLLs that control internal logic.
0 = source clock is REFCLKP/REFCKLN
1 = source clock is PCLK (default mode).
LK_DN_RST_BYPASS#
Link Down Reset Bypass: Disables the full chip reset that would normally be
caused by a PCI Express Link Down or PCI Express Hot Reset. Refer to Section
17.2.1, “Fundamental Reset” on page 770 for reset descriptions.
0 = Do not reset on Link Down
1 = Reset on Link Down (default mode)
Table 518. Reset Strap Signals (Sheet 2 of 2)
Name Description