Intel CONTROLLERS 413808 - Manual (Page 747)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 747
PMON Unit—Intel ® 413808 and 413812
16.5.6 PMON Memory Mapped Registers
The memory mapped registers of PMON unit are accessible by the Intel XScale
®
core.
The first set of registers provide the control of the PMON unit for selecting events to
monitor and for data sampling. Each counter has one command, one events, one
status, and one data register associated with it. These registers are numbered 0
through 7.
The location of these registers are specified as a relative offset to a 512KB aligned
global PMMR offset. The default for the 512KB aligned offset is 0 FFD8 0000H defined
by the PMMRBAR register. See also Chapter 19.0, “Peripheral Registers” .
The Internal Bus Address Offset to PMMRBAR of any PMON Register can be derived by
adding the 8 KB address aligned Memory Mapped Register Range Offset ( Table 490,
“PMON Internal Bus Memory Mapped Register Range Offsets” on page 747 ) to the
Register Offset ( Table 491, “PMON Register Summaries” on page 748 )
For example the offset to PMMRBAR of the “ PMON Command Register 0” would be
(1 A000H+004H) or 1 A004H.
T
Table 490. PMON Internal Bus Memory Mapped Register Range Offsets
PMON Memory Mapped Address Range Offset
(Relative to PMMRBAR)
+1 A000H