Intel CONTROLLERS 413808 - Manual (Page 407)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 407
Messaging Unit—Intel
®
413808 and 413812
4.6.2 MSI-X Capability and Table Structures
Similar to MSI Capability, when a host processor enables Message-Signaled Interrupts
(MSI-X) on the 4138xx ATU function, the ATU function (MU) is responsible to signal
interrupt to the host via a PCI write instead of the assertion of the P_INTA# output
pin.
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a states that
“PCI-X devices that generate interrupts are required to support message-signaled
interrupts, as defined by the PCI Local Bus Specification, Revision 2.2 and must support
a 64-bit message address.” “Devices that require interrupts in systems that do not
support message-signaled interrupts, must implement interrupt pins.” Thus, the
4138xx needs to implement both wired and message-signaled interrupt delivery
mechanisms.
In support of MSI-X, the 4138xx implements the MSI-X capability structure. The
capability structure includes the “MSI-X Capability Identifier Register - MSI-X_Cap_ID”
on page 435 , the “MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr” on
page 436 , the “MSI-X Message Control Register - MSI-X_MCR” on page 437 , the “MSI-X
Table Offset Register — MSI-X_Table_Offset” on page 438 and the “MSI-X Pending Bit
Array Offset Register - MSI-X_PBA_Offset” on page 439 .
During system initialization, the configuration software for an MSI-X system reads the
Message Control Register to determine that the 4138xx is capable of generating eight
unique interrupt messages by reading the MSI-X table size. The configuration software
also reads the MSI-X Table offset Register and MSI-X Pending Bits Array Register to
determine the locations these structures.
After gathering this data from all of the MSI-X capable devices in the system, the
configuration software decides how to initialize the MSI-X Table by writing the Message
Address Registers (and the Message Upper Address Registers when Message Address is
above the 4G address boundary
13
), the Message Data Registers, and the Vector Control
Registers in order to unmask a Table entry. This system specified data is used to route
the interrupt request message to the appropriate entry in a host processor’s Local APIC
table.
Configuration of MSI-X completes with a write to the MSI-X Message Control Register
which includes an update to the Multiple Message Enable field.
The MU on 4138xx is able to handle generating up to eight unique messages,
representing all of Outbound Doorbell Interrupts. Each outbound interrupt on the MU
has a unique MSI-X message associated to it. The MU can also be setup to generate
only a single MSI-X message. A single MSI-X message is generated when the MU MSI-X
Single Message Vector bit is set in the “MU MSI-X Control Register X — MMCRx” on
page 440 .
Note: The MU can signal an interrupt (MU MSI-X Table Write Interrupt) to the 4138xx
interrupt controller when the Host processor writes any entry in the MU MSI-X Table.
The MU MSI-X Table includes the following fields: the Message Address Registers, the
Message Upper Address Registers, the Message Data Registers, and the Vector Control
Registers. The interrupt can be enabled or disabled using the “Inbound Interrupt Mask
Register - IIMR” , and interrupt is posted in the “Inbound Interrupt Status Register -
IISR” .
13.When host software writes the Message Upper address register to a non-zero value, device
hardware uses a write transaction with a Dual Address Cycle (DAC) to present the full 64-bit
address to the bus.