Figure 85, Figure 83, Smbus interface unit—intel – Intel CONTROLLERS 413808 User Manual
Page 651: Intel
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
651
SMBus Interface Unit—Intel
®
413808 and 413812
Figure 83. DWORD Configuration Read Protocol (SMBus Word Write/Word Read, PEC
Disabled)
Figure 84. DWORD Memory Read Protocol (SMBus Word Write/(Word, Byte) Read, PEC
Enabled)
Figure 85. DWORD Memory Read Protocol (SMBus Word Write/Byte Read, PEC Enabled)
S
11X0_XXX
W A
Cmd = 10110001
A
Dest Mem
A
Add Offset[23:16]
A
PEC
S
11X0_XXX
W A
Cmd = 01110001
A
Add Offset[15:8]
A P
S
11X0_XXX
W A
Cmd = 10110000
Sr
11X0_XXX
R A
Status
S
11X0_XXX
W A
Cmd = 00110000
A
Sr
11X0_XXX
R A
Data[31:24]
A
PEC
N P
A
A
PEC
N P
A
Add Offset[7:0]
A
PEC
CLOCK STRETCH
A P
S
11X0_XXX
W A
Cmd = 00110000
A
Sr
11X0_XXX
R A
Data23:16]
A
PEC
N P
S
11X0_XXX
W A
Cmd = 00110000
A
Sr
11X0_XXX
R A
Data15:8]
A
PEC
N P
S
11X0_XXX
W A
Cmd = 01110000
A
Sr
11X0_XXX
R A
Data[7:0]
A
PEC
N P