Intel CONTROLLERS 413808 - Manual (Page 180)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
180 Order Number: 317805-001US
10
Varies with
external state
of P_M66EN
at PCI bus
reset
Conventional PCI Bus Operating at 66 MHz - When set, the interface has been initialized to function at
66 MHz in Conventional PCI mode by the assertion of P_M66EN during bus initialization. When clear,
the interface has been initialized as a 33 MHz bus.
Note: When PCSR bits 19:16 are not equal to zero, then this bit is meaningless since the4138xx is
operating in PCI-X mode.
09 PMODE2
PCI Bus Mode 2
Indicates the bus is capable of operating in PCI-X Mode 2.
08
Varies with
external state
of
P_REQ64#
at PCI bus
reset
PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been configured as 64-bit capable by
the assertion of P_REQ64# on the rising edge of P_RST# . When set, the PCI interface is configured
as 32-bit only. Note that this bit is valid only when acting as an endpoint.
07
Varies with
external state
of the
FW_TIMER_
OFF#
strap
Firmware Timer Disable
0 = Firmware Timeout is disabled.
1 = Firmware Timeout is enabled
When enabled, a 400mS timer is started at the trailing edge of reset. The Configuration Request Retry
bit (bit 2 of this register) is cleared when it is not cleared before the expiration of the timer. For
example, when firmware does not clear the Configuration Request Retry bit before the timer expires.
The firmware timer bit is also automatically cleared by the firmware timer when the Configuration
Request Retry bit is still set when the timer expires. After the host is allowed access, the firmware timer
bit can be used to indicate how the Configuration Request Retry bit was cleared:
0 = The firmware timer expired and cleared both the Configuration Request Retry and the firmware
timer bits.
1 = Firmware cleared the Configuration Request Retry bit before the timer expired.
Note: When the firmware timer is disabled, firmware is responsible to clear the Configuration Request
Retry bit. Otherwise, the ATU indefinitely retries all host configuration cycles.
06:03 00
2
Reserved
02
Varies with
external state
of RETRY pin
at PCI bus
reset
Configuration Cycle Retry - When this bit is set, the PCI interface of the 4138xx responds to all
configuration cycles with a Retry condition. When clear, the 4138xx responds to the appropriate
configuration cycles.
The default condition for this bit is based on the external state of the RETRY pin at the rising edge of
P_RST# . When the external state of the pin is high, the bit is set. When the external state of the pin is
low, the bit is cleared.
01:00
Varies with
external state
of the
RST_MODE
[1:0]#
pins at PCI
bus reset
Core Processor Reset - These bits are set to their default values by the hardware when either P_RST#
is asserted or the Reset Internal Bus bit in PCSR is set. When these bits are set, the associated Intel
XScale ® processors are being held in reset. Software cannot these bits. Software is required to clear
these bit(s) to deassert Intel XScale ® processor reset.
The default condition for these bits are based on the external state of the RST_MODE[1:0]# pins at
the rising edge of P_RST# . When the external state of these pins are low, the default value of these
bits is set. When the external state of the pin is high, the default value of these bits is clear.
Note: RST_MODE0# is associated with Intel XScale ® processor 0 which is the Protocol Core while
RST_MODE1# is associated with Intel XScale ® processor 1 which is the Application core.
Table 68. PCI Configuration and Status Register - PCSR (Sheet 3 of 3)
Bit Default Description
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
rw
rw
rc
rc
rw
rw
rw
rw
rw
rw
rw
rw
ro
ro
ro
ro
rv
rv
rw
rw
rv
rv
ro
ro
ro
ro
ro
ro
rc
rc
rv
rv
rv
rv
rv
rv
rv
rv
rw
ro
co
co
co
co
Attribute Legend:
RV = Reserved
CO = Clear Only
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+074H