Intel CONTROLLERS 413808 - Manual (Page 509)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 509
System Controller (SC) and Internal Bus Bridge—Intel
®
413808 and 413812
03:02 00
2
Error Type: This field specifies the error type:
00 Master Abort
01 Bridge Master Address Error
10 Target Abort
11 Target Address Error
Note: Bridge Master Address Error is an error condition that the Bridge detects when acting as a
Master on either interface. Target Address Error is an error condition indicating that any target
(including the bridge) on the south internal bus has detected an Address Error.
Note: Since the Bridge can potentially detect two errors simultaneously — one error per interface, the
Bridge only logs one of the errors as there is only one set of log registers.
01 0
2
Error N Detected: Indicates that the Bridge detected an error on either the north or south internal bus
interface while BECSR[0] was set.
0 = No error detected
1 = Error detected
00 0
2
Error Detected: Indicates that the Bridge detected an error on either the north or south internal bus.
0 = No error detected
1 = Error detected and recorded in BAR and BUAR.
Table 342. Bridge Error Control and Status Register — BECSR (Sheet 2 of 2)
Bit Default Description
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rv
na
rv
na
rv
na
rv
na
ro
na
ro
na
ro
na
ro
na
rv
na
rv
na
ro
na
ro
na
ro
na
ro
na
rc
na
rc
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
South XBG
internal bus address offset
+178CH