Intel CONTROLLERS 413808 - Manual (Page 54)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
54 Order Number: 317805-001US
Inbound and outbound ATU transactions are best described by the data flows used on
the PCI bus and the 4138xx internal bus during read and write operations. The
following sections describe read and write operations for inbound ATU transactions (PCI
to internal bus) and outbound transactions (internal bus to PCI).
Table 3. ATU Command Support
PCI Command
Encoding
PCI Command
Type
PCI-X
Command
Type
Claimed on
Inbound
Transactions
on PCI Bus
Generated by
Outbound
Transactions
on PCI Bus
Valid Internal
Bus Command
0000
Interrupt
Acknowledge
Interrupt
Acknowledge
No No Reserved
0001 Special Cycle Special Cycle No No Reserved
0010 I/O Read I/O Read No 1 Yes Reserved
0011 I/O Write I/O Write No 1 Yes Reserved
0100 Reserved Reserved No No Reserved
0101 Reserved
Device ID
Message 2
No No Reserved
0110 Memory Read
Memory Read
DWORD
Yes Yes Read
0111 Memory Write Memory Write Yes Yes Write
1000 Reserved
Alias to Memory
Read Block
Yes No Read
1001 Reserved
Alias to Memory
Write Block
Yes No Write
1010
Configuration
Read
Configuration
Read
Yes Yes Read
1011
Configuration
Write
Configuration
Write
Yes Yes Write
1100
Memory Read
Multiple
Split Completion Yes Yes Split Completion
1101
Dual Address
Cycle
Dual Address
Cycle
Yes Yes Reserved
1110
Memory Read
Line
Memory Read
Block
Yes Yes
3
Read
1111
Memory Write
and Invalidate
Memory Write
Block
Yes Yes Write
Notes:
1. The ATUX function itself does not claim I/O Transactions.
2. PCI-X mode 2 only
3. PCI-X mode only