Intel CONTROLLERS 413808 - Manual (Page 105)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 105
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.7.3.9.2 PCI-X Mode
Uncorrectable Data errors occurring during configuration write operations received by
the ATU may cause PERR# assertion and delivery of a Split Completion Error Message
on the PCI Bus. When an error occurs, the ATU accepts the write data and complete
with a Split Response Termination. Specifically, the following actions with the given
constraints are then taken by the ATU:
• When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three
clocks cycles following the Split Response Termination in which the uncorrectable
data error is detected on the bus. When the ATU asserts PERR# , additional actions
are taken:
— An Uncorrectable Split Write Data Error message (with message class=2h -
completer error and message index=01h - Uncorrectable Split Write Data
Error) is initiated by the ATU on the PCI bus that addresses the requester of the
configuration write.
— When the Initiated Split Completion Error Message Interrupt Mask in the
ATUIMR is clear, set the Initiated Split Completion Error Message bit in the
ATUISR. When set, no action.
— The Split Write Request is not enqueued and forwarded to the internal bus.
• The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit,
additional actions are taken:
— When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear,
set the Detected Parity Error bit in the ATUISR. When set, no action.
• For PCI-X Mode 2, update the “ECC Control and Status Register - ECCCSR” on
page 195 , the “ECC First Address Register - ECCFAR” on page 198 , the “ECC
Second Address Register - ECCSAR” on page 199 , and the “ECC Attribute Register -
ECCAR” on page 200 for the transaction.