Intel, Pmon, Bit default description – Intel CONTROLLERS 413808 User Manual
Page 750
Intel
®
413808 and 413812—PMON Unit
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
750
Order Number: 317805-001US
24
0b
Threshold Indicator Enable (THIE)
0 = No indication provided when threshold condition is true except for setting the Threshold Indicator
(TI) status bit.
1 = When the threshold condition is true, the counter sets the status bit and possibly assert the
PMON
OUT pin or enable the generation of an interrupt. This is controlled by the
PMON
OUT Enable
and Interrupt Enable respectively. Interrupts are driven directly off of the status bits, whereas the
PMON
OUT pin is driven directly from the condition.
23:21
000b
Condition Code (CC)
This field contains the code that indicates what type of threshold compare is done between the counter
and the data register. For all non-0 values of this field, the counter’s data register contains the
threshold value. The outcome of this compare generates a threshold event and potentially an interrupt
when that capability is enabled.
• Bit 23 is for less than (<)
• Bit 22 is for equal (=)
• Bit 21 is for greater than (>)
Select the proper bit mask for desired threshold condition:
• 000 = False (no threshold compare)
• 001 = Greater Than
• 010 = Equal
• 011 = Greater Than or Equal
• 100 = Less Than
• 101 = Not Equal
• 110 = Less Than or Equal
• 111 = True (always generate threshold event)
20
0b
Select ALL Counters (SAC). This bit controls how the opcode in bits 19:16 is applied to all counters. The
rest of the
PMON
_CMD register is not affected by the setting of this bit.
0 = The opcode is applied only to the counter associated with this command register.
1 = The opcode is applied to ALL counters. This means that every command register is written to with
the same value that was written to this particular command register. This is particularly useful for
resetting all counters with a single command or starting or stopping all counters simultaneously.
Note:
This bit is only valid in Command Register 0 and has no effect in non-0 command registers.
“Globally” executed commands (by setting this bit in Command Register 0) always override
“locally” executed commands.
Table 492. PMON Command Register 0-7 - PMON_CMD[0:7] (Sheet 2 of 4)
Bit
Default
Description
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rv
rv
rv
rv
rv
rv
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
PMON
_CMD0
PMON
_CMD1
PMON
_CMD2
PMON
_CMD3
PMON
_CMD4
PMON
_CMD5
PMON
_CMD6
PMON
_CMD7
+000h
+010h
+020h
+030h
+040h
+050h
+060h
+070h