Intel CONTROLLERS 413808 - Manual (Page 657)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 657
SMBus Interface Unit—Intel ® 413808 and 413812
12.4.5 SMBus Controller ADDR1 Register Number — SM_ADDR1
This register should be programmed with the upper address bits (bits [11:8]) of the
Register Number of the desired configuration register for 4-KByte configuration space.
4138xx ignores bit [7:4] of this register. The Status Register should be checked to
make sure that there is not a command currently in progress, before writing to this
register. Writing to this register when the 'Busy' bit in the Status Register is asserted
has indeterminate effects. When accessing memory space, ADDR1 provides bits [15:8]
of the memory address offset.
12.4.6 SMBus Controller ADDR0 Register Number — SM_ADDR0
This register should be programmed with the lower address bits (bits [7:0]) of the
Register Number of the desired configuration register for 4-KByte configuration space.
The Status Register should be checked to make sure that there is not a command
currently in progress, before writing to this register. Writing to this register when the
'Busy' bit in the Status Register is asserted has indeterminate effects. When accessing
memory space, SM_ADDR0 provides bits [7:0] of the memory address offset.
Table 438. SMBus Controller ADDR1 Register Number — SM_ADDR1
Bit Reset Description
07:00 00H
Upper Number (UNUM): Indicates the upper 4 bits (bits [11:8] of the register number to access for
4-KByte configuration space. Bits [7:4] of this registers is ignored by 4138xx. For memory access, this
register provides bits [15:8] of the memory address offset.
Table 439. SMBus Controller ADDR0 Register Number — SM_ADDR0
Bit Reset Description
07:00 00H
Lower Number (LNUM): Indicates the lower 8 bits (bits [7:0] of the register number to access for
4-KByte configuration space. For memory access, this register provides bits [7:0] of the memory
address offset.