Intel CONTROLLERS 413808 - Manual (Page 428)

Intel
®
413808 and 413812—Messaging Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
428 Order Number: 317805-001US
4.7.18 MU MSI-X Table Message Vector Control Registers -
M_MT_MVCR[0:7]
The MU MSI-X Table Message Vector Control Register contains the mask bit for this
entry in the MSI-X Table. An entry in the MSI-X Table is made up of four DWORDs.
Note: The M_MT_MVCR[0:7] registers are not reset with an internal bus reset.
Table 283. MU MSI-X Table Message Vector Control Registers - M_MT_MVCR [0:7]
Bit Default Description
31:01 0000 0000H Reserved.
00 1
2
Message Vector Control: This bit when set, prohibits the sending an MSI-X message using this entry.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw
rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
M_MT_MAR0
M_MT_MAR1
M_MT_MAR2
M_MT_MAR3
M_MT_MAR4
M_MT_MAR5
M_MT_MAR6
M_MT_MAR7
internal bus address
offset
500CH
501CH
502CH
503CH
504CH
505CH
506CH
507CH
M_MT_MAR0
M_MT_MAR1
M_MT_MAR2
M_MT_MAR3
M_MT_MAR4
M_MT_MAR5
M_MT_MAR6
M_MT_MAR7
MU/PCI Base Address
Offset
100CH
101CH
102CH
103CH
104CH
105CH
106CH
107CH