Intel, Bit default description, 30 0h – Intel CONTROLLERS 413808 User Manual
Page 450
Intel
®
413808 and 413812—SRAM DMA Unit (SDMA)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
450
Order Number: 317805-001US
5.4.5
LocalToHost Interrupt Counter/Acknowledge Register
L2H_ICAR
Firmware uses the LocalToHost Interrupt Counter/Acknowledge Register (L2H_ICAR) to
keep track of and acknowledge interrupts.
Table 303. LocalToHost Interrupt Counter/Acknowledge Register - L2H_ICAR
Bit
Default
Description
31:30
0H
Reserved
29:24
000000
2
Interrupt Counter - Read Only
The Interrupt Counter is a counter of the number of interrupts on this DMA channel. It is monotonically
increasing (by 1) and wraps around to zero after reaching its maximum value. When a DMA completes
for this channel, the Interrupt Counter is incremented and an interrupt is asserted. Firmware reads the
Interrupt Counter of each channel to determine which one raised the interrupt. Firmware then writes
back the Interrupt Counter value to the Interrupt Acknowledge to clear the interrupt.
23:06
0000H
Reserved
05:00
00H
Interrupt Acknowledge - Read/Write
The Interrupt Acknowledge is used to clear interrupts. Firmware reads the Interrupt Counter and then
writes that value back to the Interrupt Acknowledge field.
Coprocessor
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rv
ro
rv
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
rv
ro
rv
ro
rv
ro
rv
ro
rv
ro
rv
ro
rv
ro
rv
ro
ro
ro
rv
ro
rv
ro
rv
ro
rv
ro
rv
ro
rv
ro
rv
ro
rv
ro
rv
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal bus address offset
18238H