48 pm capability identifier register - pm_cap_id, 48pm capability identifier register - pm_cap_id, 49pm next item pointer register - pm_next_item_ptr – Intel CONTROLLERS 413808 User Manual

Page 187: 75 pm_capability identifier register - pm_cap_id, Section 2.14.49, Address translation unit (pci-x)—intel, Bit default description

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413808 and 413812 I/O Controllers in TPER Mode

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187

Address Translation Unit (PCI-X)—Intel

413808 and 413812

2.14.48 PM Capability Identifier Register - PM_Cap_ID

The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus

Specification, Revision 2.3. This register in the PCI Extended Capability header

identifies the type of Extended Capability contained in that header. In the case of the

4138xx, this is the PCI Bus Power Management extended capability with an ID of 01H

as defined by the PCI Bus Power Management Interface Specification, Revision 1.1.

2.14.49 PM Next Item Pointer Register - PM_Next_Item_Ptr

The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus

Specification, Revision 2.3. This register describes the location of the next item in the

function’s capability list. For the 4138xx, the next capability (MSI-X capability list) is

located at off-set B0H. Note that the PM_Next_Item_Ptr can be written by the

processor.

Table 75. PM_Capability Identifier Register - PM_Cap_ID

Bit

Default

Description

07:00

01H

Cap_Id

- This field with its’ 01H value identifies this item in the linked list of Extended Capability

Headers as being the PCI Power Management Registers.

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

PCI Configuration Offset

98H

+098H

Table 76. PM Next Item Pointer Register - PM_Next_Item_Ptr

Bit