Intel CONTROLLERS 413808 - Manual (Page 621)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 621
Interrupt Controller Unit—Intel
®
413808 and 413812
10.7.27 Interrupt Priority Register 2 — IPR2
The Interrupt Priority Register 2 is a 32-bit Coprocessor 6 control register used to
assign a priority level to interrupt sources 47 down to 32. The IPR2 control register is
used to assign one of 4 priority levels to each interrupt source independent of the
INTSTR[3:0] registers:
When interrupt vector generation is enabled and there are multiple requests pending
either in the FINTSRC[3:0] or the IINTSRC[3:0] registers, the highest priority vectors
pending for either FIQ or IRQ are presented in the FINTVEC or IINTVEC respectively.
Note: When multiple interrupts at the same priority level are pending for either FIQ or IRQ,
the vector is selected according to a fixed priority based on bit location. Highest order
bit is first.
00
2 —
High Priority
01
2 —
Medium/High Priority
10
2 —
Medium/Low Priority
11
2 —
Low Priority
Table 409. Interrupt Priority Register 2 — IPR2
Bit Default Description
31:16 00H Reserved.
15:14 00
2
XINT15# Interrupt Priority
13:12 00
2
XINT14# Interrupt Priority
11:10 00
2
XINT13# Interrupt Priority
09:08 00
2
XINT12# Interrupt Priority
07:06 00
2
XINT11# Interrupt Priority
05:04 00
2
XINT10# Interrupt Priority
03:02 00
2
XINT9# Interrupt Priority
01:00 00
2
XINT8# Interrupt Priority
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, Page 8, Register 2