Intel CONTROLLERS 413808 - Manual (Page 498)

Intel
®
413808 and 413812—System Controller (SC) and Internal Bus Bridge
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
498 Order Number: 317805-001US
7.5 Internal Bus Bridge Register Definitions
The following registers are located in the Peripheral Memory-Mapped Register (PMMR)
address space. They are only accessible from the south internal bus. Accesses to the
Bridge registers that originate from the north internal bus are propagated to the south
internal bus, and then claimed by the Bridge on the south interface. The Bridge Error
Status register indicates the type of error that was encountered by the bridge on either
the north or south interfaces. The Bridge Error Address and Error Upper Address
registers indicate the address of the request that encountered the error. The Bridge
Window Base Address and Window Limit Registers together define a memory window
for the Bridge to claim transactions on the south internal bus.
• Bridge Window Base Address Register
• Bridge Widow Upper Base Address Register
• Bridge Window Limit Register
• Bridge Error Status Register
• Bridge Error Address Register
• Bridge Error Upper Address Register
The internal bus bridge only claims the address offset range +1780H through +1797H.