Intel CONTROLLERS 413808 - Manual (Page 204)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
204 Order Number: 317805-001US
2.14.64 Inbound ATU Base Address Register 3 - IABAR3
The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU
Upper Base Address Register 3 (IAUBAR3) defines the block of memory addresses
where the inbound translation window 3 begins. The inbound ATU decodes and
forwards the bus request to the 4138xx internal bus with a translated address to map
into 4138xx local memory. The IABAR3 and IAUBAR3 define the base address and
describe the required memory block size; see Section 2.14.23, “Determining Block
Sizes for Base Address Registers” on page 164 . Bits 31 through 12 of the IABAR3 is
either read/write bits or read only with a value of 0 depending on the value located
within the IALR3. This configuration allows the IABAR3 to be programmed per PCI Local
Bus Specification, Revision 2.3.
The programmed value within the base address register must comply with the PCI
programming requirements for address alignment. Refer to the PCI Local Bus
Specification, Revision 2.3 for additional information on programming base address
registers.
Note: Since IABAR3 does not appear in the standard PCI configuration header space (offsets
00H - 3CH), IABAR3 is not configured by the host during normal system initialization.
Warning:
When a non-zero value is not written to IALR3, the user should not set either the
Prefetchable Indicator or the Type Indicator for 64 bit addressability. This is the default
for IABAR3. Assuming a non-zero value is written to IALR3, the user may set the
Prefetchable Indicator or the Type Indicator:
a. Since non prefetchable memory windows can never be placed above the 4 Gbyte
address boundary, when the Prefetchable Indicator is not set, the user should
also leave the Type Indicator set for 32 bit addressability. This is the default for
IABAR3.
b. For compliance to the PCI-X Protocol Addendum to the PCI Local Bus
Specification, Revision 2.0, when the Prefetchable Indicator is set, the user
should also set the Type Indicator for 64 bit addressability.
Table 91. Inbound ATU Base Address Register 3 - IABAR3
Bit Default Description
31:12 00000H
Translation Base Address 3 - These bits define the actual location the translation function is to respond
to when addressed from the PCI bus.
11:04 00H Reserved.
03 0
2
Prefetchable Indicator - When set, defines the memory space as prefetchable.
02:01 00
2
Type Indicator - Defines the width of the addressability for this memory window:
00 - Memory Window is locatable anywhere in 32 bit address space
10 - Memory Window is locatable anywhere in 64 bit address space
00 0
2
Memory Space Indicator - This bit field describes memory or I/O space base address. The ATU does not
occupy I/O space, thus this bit must be zero.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
ro
rw
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+200H