Intel CONTROLLERS 413808 - Manual (Page 102)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
102 Order Number: 317805-001US
2.7.3.7 Outbound Read Completion Uncorrectable Data Errors
As a target, the ATU may encounter this error when operating in the PCI-X mode.
Uncorrectable Data errors occurring during read completion transactions that are
claimed by the ATU are recorded, PERR# is asserted (when enabled) and SERR# is
asserted (when enabled). Specifically, the following actions with the given constraints
are taken by the ATU:
• PERR# is asserted two clocks cycles (three clock cycles when operating in the
PCI-X mode) following the data phase in which the uncorrectable data error is
detected on the bus. This is only done when the Parity Error Response bit in the
ATUCMD is set. When the ATU asserts PERR# , additional actions are taken:
— The Master Parity Error bit in the ATUSR is set.
— When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear,
set the PCI Master Parity Error bit in the ATUISR. When set, no action.
— When the SERR# Enable bit in the ATUCMD is set, and the Uncorrectable Data
Error Recover Enable bit in the PCIXCMD register is clear, assert SERR# ,
otherwise no action. When the ATU asserts SERR#, additional actions are
taken:
Set the SERR# Asserted bit in the ATUSR.
When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set
the SERR# Asserted bit in the ATUISR. When set, no action.
When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set
the SERR# Detected bit in the ATUISR. When clear, no action.
— The read completion is aborted on the internal bus of the 4138xx.
• The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit,
additional actions are taken:
— When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear,
set the Detected Parity Error bit in the ATUISR. When set, no action.
• For PCI-X Mode 2, update the “ECC Control and Status Register - ECCCSR” on
page 195 , the “ECC First Address Register - ECCFAR” on page 198 , the “ECC
Second Address Register - ECCSAR” on page 199 , and the “ECC Attribute Register -
ECCAR” on page 200 for the transaction.