Intel CONTROLLERS 413808 - Manual (Page 441)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 441
Messaging Unit—Intel
®
413808 and 413812
4.7.32 Inbound MSI Interrupt Pending Register x — IMIPRx
The Inbound MSI Interrupt Pending register is a 32-bit register that is used to post the
one-hot decoded bits that are generated by the MU (Messaging Unit) when receiving
inbound MSI (Message-Signaled Interrupt). The MU can generate up to 128 interrupts.
Refer to the MSI Inbound Message Register — MIMR in the MU Chapter. Any bit set in
this register generates an interrupt to the Intel XScale
®
processor via the Inbound MSI
Interrupt pending signal. Software must clear this register to clear any pending
interrupt.
4.8 Power/Default Status
The software is responsible for initializing the Circular Queue Size in the MU
Configuration Register and all head and tail pointer registers before setting the Circular
Queue Enable bit.
Table 297. Inbound MSI Interrupt Pending Registers — IMIPR [0:3]
Bit Default Description
31:00 0000 0000H
Inbound MSI Pending Interrupts — Each bit reflects an inbound MSI interrupt that was generated by the
MU (Messaging Unit). The MU receives, decodes and generates a one-hot bit for every MSI message
that it receives. Any bit set generates an interrupt to the Intel XScale ® processor via the Inbound MSI
Interrupt Pending signal.
Memory
Co-Processor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
rc
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor
Local Bus Address Offset
coreID0 - n/a
coreID1 - n/a
Intel XScale ® processor Coprocessor Address
IMIPR 0: CP6, CRm 1, CRn 8
IMIPR 1: CP6, CRm 1, CRn 9
IMIPR 2: CP6, CRm 1, CRn 10
IMIPR 3: CP6, CRm 1, CRn 11